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Slowdown, what slowdown? TSMC is ramping up

By Bill Ray | September 01, 2020 | 0 Comments

TSMC – the world’s largest semiconductor fabrication company – is ramping up production and tech investment, at a time when some might be battening down the hatches. The company has been told, by the US government no less, that is mustn’t supply chips to one of its biggest customers (Huawei), meanwhile the world is facing a global slowdown as the economic impact of the pandemic hits. Yet things over at TSMC are just peachy, with full order books and huge investments in advancing technology, as my colleague Samuel Tuan Wang found out at the company’s (virtual) Technology Symposium.

Since the end of 2019 most Asian foundries have been reporting high utilisation at 200mm, driven by the increased demand of PMIC, Display Drives, CIS and Power IC for 5G products. Rumours say that TSMC’s capacity is oversubscribed by 60% or more, and the efforts the company is taking would seem to bear that out. TSMC’s plan is to push customers into migrating RF from 16nm to 6nm, CIS from 22nm to 16nm and PMIC from 0.11um to 40nm, and then expanding its “Fab 14” to increase production. TSMC will encourage many of its 200mm customers to migrate their products to 300mm wafers which have significant cost advantage.

At the symposium the company showed that it’s capacity for sub-20nm chips has been increasing at 28% CAGR. In 2020, 7nm capacity will be three times what it was in 2018, while the capacity of 5nm in 2021 will be twice what it is in 2020.

Not only are today’s products selling, but TSMC is pushing towards the future at a breakneck pace. The current cutting edge is 5nm, but TSMC detailed a 3nm process which will be in volume production in the second half of 2022. All this using FinFET, and back filling with odd notes (6nm, 4nm) and derivative technologies such as an ultra-low-power option.

Even more impressive is the yield improvement reported by TSMC that the D0 defect density of N5 (the 5nm node) is approaching 0.1 defects per square inch per photo layer, beating its 7 nm node N7 at the same stage of development.

But smaller geometries will only get you so far. In the past few years, a combination of increased process complexity and rising cost of production has challenged the economic benefit of Moore’s Law. Heterogeneously integrated packaging technology will be increasingly important for faster time to market, higher yield and lower cost by adopting small die sized chiplets, not to mention adding the ability to source best performing chiplets from different vendors. TSMC will invest close to $10B in a backend fab in ZhuNan (Taiwan) capable of exploiting these techniques, with production commencing by the middle of 2021.

At the symposium TSMC was also promoting its “3DFabric” – silicon stacking with advanced packaging. By adopting organic RDL, silicon interconnect to both 2.5D and 3D configuration, new flavours of InFO (Integrated Fan Out) and CoWoS (Chip on Wafer on Substrate) TSMC is matching up with both Intel and Samsung in offering advanced wafer level package.

All this technology is expensive; TSMC’s spending on research and development jumped from $2.85B in 2018 to $2.96B in 2019, but it demonstrates TSMC’s commitment to continuous advancing logic process – down to 2nm and beyond. This spending is predicated on the idea that the economy is going to rebuild, that we’ll see a 5G phone in every pocket, and two connected cars in every garage. TSMC sees a bright future, and has the order book to back up that view, so perhaps the rest of us should stop being so damn pessimistic?

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